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Spatial Charge Trap Engineering with Boron Nitride Barrier for 3D V-NAND Flash Memory

Journal: 2024 International Electron Devices Meeting (IEDM)

Author: Dae Hyun Kang, Jae Joong Jeong, Young Keun Park, Dong Hun Sin, Han Mei Choi and Byung Jin Cho

Year: 2024

Date: Dec. 2024

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"Spatial Charge Trap Engineering with Boron Nitride Barrier for 3D V-NAND Flash Memory", 2024 International Electron Devices Meeting (IEDM)

Dae Hyun Kang¹, Jae Joong Jeong¹, Young Keun Park¹, Dong Hun Sin², Han Mei Choi² and ^*Byung Jin Cho¹

¹School of Electrical Eng., KAIST, Korea

²Semiconductor R&D Center, Samsung Electronics, Korea

^*email: bjcho@kaist.edu