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Total 331건 16 페이지

2007
106

"Impact of interfacial layer control using Gd2O3 in HfO2 gate dielectric" G. K. Kalapati, Y. Tong, W. Y. Loh, H. K. Mun, and B. J. Cho, Appl. Phys. Lett., May. 2007..
105

"Complementary Metal-Oxide-Semiconductor compatible Al-catalyzed silicon nanowires" S. J. Whang, S. J. Lee, W. F. Yang, B. J. Cho, Y. F. Liew, and D. L. Kwong, Electrochem. and Solid-State Lett., Mar. 2007..
104

"Border-Trap CharacteNrization in High-K Strained-Si MOSFETs" D. Maji, S. P. Duttagupta, V. R. Rao, C. C. Yeo, and B. J. Cho, IEEE Electron Device Lett., Aug. 2007..
103

"Study on the synthesis of high quality single crystalline SixGex nanowire and its transport properties" S. J. Whang, Sungjoo Lee, W. F. Yang, B. J Cho, and D. L. Kwong, Appl. Phys. Lett., Aug. 2007..
102

"Strained Si/SiGe channel with buried Si0.99C0.01 for improved drivability, gate stack integrity and noise performance" W. Y. Loh, H. Zang, H. J. Oh, K. J. Choi, H. S. Nguyen, G. Q. Lo, and B. J. Cho, IEEE TRANSACTIONS ON ELECTRON DEVICES, Dec. 2007..
101

"Tensile-Strained Germanium CMOS Integration on Silicon" H. Zang, W. Y. Loh, J. D. Ye, G. Q. Lo, and B. J. Cho,, IEEE Electron Device Lett, Dec. 2007..
100

"Integration of GaAs epitaxial layer to Si-based substrate using Ge condensation and low-temperature migration enhanced epitaxy techniques" H. J. Oh, K. J. Choi, W. Y. Loh, T. Htoo, S. J. Chua and B. J. Cho, J. Appl. Phys., Sep. 2007..
99

"Electrical and Interfacial Characterization of Atomic Layer Deposited High-K Gate Dielectrics on GaAs for Advanced CMOS Devices" G.K.Dalapati, Y.Tong, W.Y.Loh, H.K.Mun, and B.J.Cho, IEEE Trans. on Electron. Devices, Aug. 2007..
98

"P-Type Floating Gate for Retention and P/E Window Improvement of Flash Memory Devices" C. Shen, J. Pu,M. -F. Li, and B. J. Cho, IEEE Trans. Electron Devices, Aug. 2007..
97

"Low energy N2 ion bombardment for removal of (HfO2)x(SiON)1-x in dilute HF" W. S. Hwang, B. J. Cho, D. S. H. Chan, and W. J. Yoo, J. Vacuum Sci. and Technol. -Section A, Jul. 2007..
2006
96

"Correlation between optical properties and Si nanocrystal formation of Si-rich Si oxide films prepared by plasma-enhanced chemical vapor deposition" X. Y. Chen, Y. F. Lu, Y. H. Wu, B. J. Cho, L. J. Tang, D. Lu, and J. R. Dong, Applied Surface Science, Dec. 2006..
95

"Effects of SiO2/Si3N4 hard masks on etching properties of metal gates" W. S. Hwang, B. J. Cho, and D. S. H. Chan, V. Bliznetsov, and W. J. Yoo, J. Vacuum sci. & technol., Dec 2006..
94

"SiGe on Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistor integrated with Schottky Source/Drain and HfO2/TaN Gate Stack" F.Gao, S. J. Lee, R. Li, B. J. Cho, S. Balakumar, Chih-Hang Tung, D. Z. Chi, and D. L. Kwong, Electrochem. and Solid-State Lett., Jul. 2006..
93

"Thermal stability study of Si cap/ultrathin Ge/Si and strained Si/Si1-xGex/Si nMOSFETs with HfO2 gate dielectric" C. C. Yeo, B. J. Cho, M. H. Lee, C. W. Liu, K. J. Choi, and T. W. Lee, Semiconductor sci. and technol., May. 2006..
92

"Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack" M. S. Joo, C. S. Park, B. J. Cho, N. Balasubramanian, and D. L. Kwong, J. Vacuum sci. & technol. B, May. 2006..

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