Abstract

 A novel memory device structure, called backside ferroelectric-assisted charge trap flash (BF-CTF), has been proposed. The ferroelectric layer at the backside of the polysilicon channel can be polarized by the front gate voltage due to the speed difference between polarization and the inversion layer generation. The backside polarization can modulate the body potential and make additional threshold voltage (Vth) shift, providing additional memory window. The BF-CTF device exhibits significantly improved memory performance such as increased memory window, reduced program/erase time, and improved charge retention. More importantly, the BF-CTF device does not suffer from read disturbance problems originated from the minor loop of ferroelectric, as the ferroelectric polarization is decoupled from the read operation.