E. J. Shin, G. Lee, S. Kim, J. H. Chu and B. J. Cho, "Dual-Mechanism Memory Combining Charge Trapping and Polarization Switching for Wide Memory Window Flash Cell," in IEEE Electron Device Letters, doi: 10.1109/LED.2023.3282366.

Abstract: We propose a novel memory device to overcome the limited Vth window in charge trap flash (CTF) memory, which prevents the realization of a high number of bits/cell. The proposed memory device (named “dual-mechanism memory”) has a ferroelectric HfZrO2 layer on the channel so that the conductance of the channel can be controlled by the remanent polarization (Pr). In addition, since trap-rich Si3N4 and tunnel SiO2 layers are located on top of the ferroelectric layer, the conductance of the channel can also be controlled by electron injection/removal from/to the gate electrode. Compared to a reference memory that uses only charge trapping, the dual-mechanism memory provided up to 96% wider memory window and exceeded the theoretical limit of ISPP slope in a conventional CTF. It also showed up to 36% improvement in retention characteristics. The enhanced retention performance is attributed to compensation of the E-field stress by Pr.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10144281&isnumber=4357973