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Border-Trap CharacteNrization in High-K Strained-Si MOSFETs
Journal
IEEE Electron Device Lett.
Author
D. Maji, S. P. Duttagupta, V. R. Rao, C. C. Yeo, and B. J. Cho
Year
2007
Date
Aug. 2007.

D.Maji, S.P.Duttagupta, V.R.Rao, C.C.Yeo, and B.J.Cho, "Border-Trap CharacteNrization in High-K Strained-Si MOSFETs," IEEE Electron Device Lett., vol. 28, no.8, pp. 731-711, Aug. 2007.