Abstract

 Among the various three-dimensional (3D) stacking techniques essential for scaling electronic devices, monolithic-3D (M3D) integration technology offers the highest integration density. However, this technology faces challenges such as sensitivity to high temperatures and electrical interference owing to the thin interlayer dielectric (ILD). In this study, we realized a 2-tier M3D structure using an MoS2 fieldeffect transistor (FET) to minimize the process temperature. This device demonstrated favorable electrical properties, such as an on-off ratio of 104, subthreshold swing of 0.286 V/dec, and on-current of 0.1 μA. In addition, ILD showed a low current of 10−11 A to isolate the device of each tier. The electrical interferences on 2-tier M3D transistor were measured by focusing on the back-gate effect when varying the ILD thickness. We used TCAD modeling to quantitatively verify the impact of the back-gate effect on the operating characteristics of the DRAM cell. The errors in the DRAM cell data were evaluated based on the swing in the bitline voltage caused by electrical interference during the read operations. We also analyzed the variation in the bitline voltage swing under the back-gate effect. The bitline voltage swing exhibited a significant change during the read operation of Data 1, whereas no such change was observed for Data 0. These results demonstrate that the accuracy of the readout data can be improved by attenuating signal interference, including crosstalk and back-gate effects. This paper quantitatively elucidates the influence of electrical interference on the operation of M3D DRAM and presents it as a key indicator for 3D stacked DRAM design.