Abstract

 We propose a novel AND-type memory array featuring a backside ferroelectric field-effect transistor (BF-FET). This architecture places the ferroelectric layer on the backside of a thin polysilicon channel. A key novelty lies in connecting all ferroelectric layers to a common back gate, which eliminates the need for an additional word line (W/L) to control the back gate bias, thereby substantially reducing design complexity. Furthermore, the BF-FET exhibits inherent immunity to read disturbance originating from the minor loop of ferroelectric materials, as its polarization switching is completely decoupled from the read operation. The BF-FET demonstrates a 3 times larger memory window than ferroelectric field effect transistors (Fe-FETs) with the same thickness of the ferroelectric and channel layers, enabling robust multi-level cell (MLC) operation. The CNN simulation demonstrates that the BF-FET-based synaptic array exhibits superior endurance, with its recognition rate remaining above 95% even after 10⁷ repeated read cycles.