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Asymmetric Memory Window Recovery Benaviorin n / p-FeFETs Revealed by Trap Analysis
Journal
IEEE Transactions on Device and Materials Reliability
Author
Bong Ho Kim, Song-Hyeon Kuk, Hyeon-Seong Hwang, Jaeyong Jeong, Youngkeun Park, Yoon-Je Suh, Joon Pyo Kim, Chan Jik Lee, Seong Kwang Kim, Dae-Myeong Geum, Byung Jin Cho, and Sang Hyeon Kim
Year
2026
Date
September 2026

 

Abstract

Ferroelectric field-effect transistor (FeFET) based on Hf0.5Zr0.5O2 (HZO) is a promising candidate for emerging memory applications. However, their practical applications of n/p-FeFETs are hindered by limited endurance. In this study, we investigate the memory window (MW) recovery characteristics of n-FeFET and p-FeFETs fabricated using an interfacial layer scavenging technique, aiming to ultimately enhance endurance characteristics. A systematic correlation between asymmetric MW recovery, carrier-dependent trap evolution, and effective response depth is established to provide mechanistic insight into the recovery behaviors of n/p-FeFETs. The underlying mechanisms are investigated through complementary analyses of trap types and effective spatial trap distribution. Specifically, n-FeFETs retained operational characteristics over 20 rounds, whereas p-FeFETs suffered breakdown after four rounds due to progressive accumulation of hole-related border traps. Our findings provide a systematic understanding of carrier-dependent trap evolution governing asymmetric MW recovery in n-FeFETs and p-FeFETs and offer key insights into designing FeFETs with improved MW recovery characteristics.