Fabrication and characterization of 65nm gate length p-MOSFET integrated with bottom up grown Si nanowire
- Year
- 2007
- Author
- W. F. Yang, S. J. Whang, S. J. Lee*, H. C. Zhu, and B. J. Cho
- Conference
- 211th Electrochemical Society Meeting
W. F. Yang, S. J. Whang, S. J. Lee*, H. C. Zhu, and B. J. Cho, "Fabrication and characterization of 65nm gate length p-MOSFET integrated with bottom up grown Si nanowire", 211th Electrochemical Society Meeting, SYMPOSIUM E1 - Advanced Gate Stack, Source/Drain and Channel Engineering for Si-Based CMOS, Chicago, May, 2007.
May, 2007.
Chicago