Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High-k/Metal Gate Stacks Directl on SiGe and a method to Enable sub-1nm EOT
- Year
- 2008
- Author
- J.Huang, P.D.Kirsch, J.Oh, S.H.Lee, J.Price, P.Majhi, H.R.Harris, D.C.Gilmer, D.Q.Kelly, P.Sivasubramani, G.Bersuker, D.Heh, C.Young, C.S.Park, Y.N.Tan, N.Goel, C.Park, P.Y.Hung, P.Lysaght, K.J.Choi, B.J.Cho, H.-H.Tseng, B.H.Lee, and R.Jammy
- Conference
- 2008 Symposium on VLSI Technology
J.Huang, P.D.Kirsch, J.Oh, S.H.Lee, J.Price, P.Majhi, H.R.Harris, D.C.Gilmer, D.Q.Kelly, P.Sivasubramani, G.Bersuker, D.Heh, C.Young, C.S.Park, Y.N.Tan, N.Goel, C.Park, P.Y.Hung, P.Lysaght, K.J.Choi, B.J.Cho, H.-H.Tseng, B.H.Lee, and R.Jammy, "Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High-k/Metal Gate Stacks Directl on SiGe and a method to Enable sub-1nm EOT", 2008 Symposium on VLSI Technology, pp82-83, Honolulu, USA, Jun., 2008.
Jun., 2008.
Honolulu, USA