Spatial Charge Trap Engineering with Boron Nitride Barrier for 3D V-NAND Flash Memory
- Year
- 2024
- Author
- Dae Hyun Kang
- Co-author
- Jae Joong Jeong, Young Keun Park, Dong Hun Sin, Han Mei Choi and Byung Jin Cho
- Conference
- 2024 International Electron Devices Meeting (IEDM)
"Spatial Charge Trap Engineering with Boron Nitride Barrier for 3D V-NAND Flash Memory", 2024 International Electron Devices Meeting (IEDM)
Dae Hyun Kang1, Jae Joong Jeong1, Young Keun Park1, Dong Hun Sin2, Han Mei Choi2 and *Byung Jin Cho1
1School of Electrical Eng., KAIST, Korea
2Semiconductor R&D Center, Samsung Electronics, Korea
*email: bjcho@kaist.edu