Abstract
High density 3D V-NAND flash memory requires charge trap layer (CTL) scaling and reliable multi-level cell operation. However, SiN CTL suffers from a charge trapping dead zone near the tunneling oxide, while SiO2/SiON/SiO2 tunneling layers show a tradeoff be-tween erase speed and reliability. In this study, we pre-sent a bandgap-engineered gate stack using BN-based dielectrics. First, a 1 nm BN barrier is inserted in the SiN CTL to enhance electron trapping in the dead zone. The scaled CTL with a BN barrier near the tunneling oxide recovers the memory window loss caused by CTL scaling. Second, the BN-based engineering concept is extended to the tunneling layer by forming BON through ozone oxi-dation. Compared with SiON, BON has a lower valence band offset (VBO) and a higher conduction band offset (CBO), enabling faster erase, improved retention, and reliable PLC operation. These results demonstrate the potential of BN-based dielectrics for gate stack engineer-ing in future 3D V-NAND flash memory.