Nano-electric Memory Device

Upcoming 5G era greatly increases the amount of data consumption with computers, IoT (Internet of Things) devices, data centers, etc. As the amount of data and communication speed increase, memory devices require faster transmission speed and larger capacity. 3D NAND Flash memory and Dynamic Random Access Memory (DRAM) are one of the key players in computer memory hierarchy, having advantages on its operating speed and data capacity.

3D NAND Flash Memory

The NAND Flash, which is one of the most significant markets in human history, has been revolutionized through stacking and XYZ-scaling aimed at increasing the memory bit density. However, the implementation of high-rise memory layers has brought about decrease in driving current, and scaling of charge trap memory cell has lead to the reliability issues (retention, endurance, disturbance) which acts as limiting the realization of PLC. To beyond these obstacles and advance further, in-depth research on NAND Flash memory (e.g. channel layer, charge trap layer and blocking oxide) is imperative to pave the way for next technological node.

Dynamic Random Access Memory

Device scaling in the DRAM industry has stalled at the 10 nm technological node due to several critical issues:
1) A physically unstable structure with a high aspect ratio,
2) An increase in leakage due to the reduction of dielectric film thickness,
3) Increased power consumption because of a shorter refresh cycle, and
4) Charge disturbances between metal lines.
To address these challenges in conventional DRAM, innovative research on both the DRAM capacitor and the transistor is required. For the DRAM capacitor, there's a need to replace the dielectric material with one that has a higher k value and offers better leakage and endurance characteristics. For the DRAM transistor, new channel materials should be explored to reduce off-current and extend the refresh cycle, ultimately leading to reduced power consumption.